A liquid crystal display (hereinafter “LCD”) includes an LCD panel formed with liquid crystal cells and pixel elements with each associating with a corresponding liquid crystal cell. These pixel elements are substantially arranged in the form of a matrix having gate lines in rows and data lines in columns. The LCD panel is driven by a driving circuit including a gate driver and a data driver. The gate driver generates a plurality of gate signals (scanning signals) sequentially applied to the gate lines for sequentially turning on the pixel elements row-by-row. The data driver generates a plurality of source signals (data signals), i.e., sequentially sampling image signals, simultaneously applied to the data lines in conjunction with the gate signals applied to the gate lines for aligning states of the liquid crystal cells on the LCD panel to control light transmittance therethrough, thereby displaying an image on the LCD.
In such a driving circuit, a shift register is utilized in the gate driver to generate the plurality of gate signals for sequentially driving the gate lines. To lower down costs, there have been efforts to integrate the shift register into an LCD panel. One of the efforts, for example, is to fabricate the shift register on a glass substrate of the LCD panel using an amorphous silicon thin film transistors (aSi TFTs), and/or low temperature polycrystalline silicon thin film transistors (LTPS TFTs).
FIG. 8 shows schematically a block diagram of an LCD 800 driven with data driver 811 and an a-Si shift register 812 having a plurality of stages S/R. The control signals 813 of the shift register includes six clock signals, CLK1, CLK2, . . . , and CLK6, a start signal, ST, applied to the first S/R stage, and a reference voltage, VSS. The shift register 812 is configured to generate a plurality of gate signals, G1, G2, . . . , Gi, according to the control signals 813 to activates pixels 814 in each row via the gate lines 815. The data driver 811 is configured to generate a plurality of data signals, D1, D2, . . . , Dj, an according to an image data, which is input to pixels 814 via data lines 816 to generate a corresponding display frame.
FIG. 9 shows a circuit diagram of a conventional a-Si shift register stage 900 having a pull-down control circuit 910. The pull-down control circuit 910 includes four transistors T4, T5, T6 and T7 electrically coupled to each other and is adapted for controlling the pull-down transistors T8 and T9. As shown in FIGS. 10 and 11, for such a configuration, in operation, the voltage difference, K(n)−P(n), between the voltages at the nodes K and P is periodically in a high voltage level for very long time. Accordingly, the transistor T5 is turned on for the durations of the high voltage level. However, when a high voltage is continually applied to the transistor T5 for a long period of time, the characteristics of the transistor T5 may deteriorate due to stress thereon and thus the transistor T5 may not function properly, thereby reducing the reliability of the shift register.
Therefore, a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies.